Reference-Ladder Free Flash Analog to Digital Converter Architecture

In this book, the primary research objective is to design a novel comparator to get rid-off reference-ladder circuit. The design of power efficient Flash ADC is investigated by utilizing a novel power optimized single-ended comparator. The proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage
generation method for producing the reference voltage for the Flash ADC design. By employing optimized comparator, the Flash ADC achieves various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate
for System-on-Chip (SoC) ADC implementation
.
The basic structure of the single-ended comparator is modified CMOS Inverter. The performance of modified CMOS Inverter circuit is compared with the static CMOS Inverter. To demonstrate the functionality of the new comparator, 4-bit and 6-bit Flash ADCs has been designed and simulated under the environment of Cadence and LTspice CAD tools. For both of the Flash ADCs, a comparative analysis is presented with previously published works on Flash ADCs.

The secondary research objective is to propose a novel power reduction technique for high-speed Flash analog-to-digital converter, which not only reduces the power consumption in comparator but also examines the inactive comparators in the Flash ADC, thus inactive comparators get shutdown to save the unnecessary power consumption.This approach is based on two-step method of data conversion. By this method the total numbers of active comparators are reduced in comparison with the conventional Flash ADC. This feature of active comparators reduces the overall power consumption of the converter and the resultant architecture develops into power efficient Flash ADC architecture.

Inhaltsverzeichnis (Table of Contents)

• Chapter 1 Introduction
  • 1.1 Overview
  • 1.2 Motivation and Research Objective
  • 1.3 book Organization
• Chapter 2 Fundamentals of comparators & Analog-to-Digital Converters
  • 2.1 Introduction
    • 2.1.1 Sampling
    • 2.1.2 Amplitude Quantization
  • 2.2 ADC Architectures
    • 2.2.1 High-Speed ADCs
      • 2.2.1.1. Flash ADC
      • 2.2.1.2. Two-Step Flash ADC
      • 2.2.1.3. Pipeline ADC
      • 2.2.1.4. Time-Interleaved ADC
    • 2.2.2 High-Resolution ADCs
      • 2.2.2.1. Successive-Approximation-Register ADC
      • 2.2.2.2. Sigma-Delta ADC
  • 2.3 ADC Specifications
    • 2.3.1 Offset & Gain Error
    • 2.3.2 Differential & Integral Non-linearity
    • 2.3.3 SNR & SNDR
    • 2.3.4 Spurious-Free-Dynamic-Range
    • 2.3.5 Effective Number of Bits
    • 2.3.6 Dynamic Range
  • 2.4 Conclusion
  • Chapter 3 Literature Review
    • 3.1 Introduction
    • 3.2 CMOS Comparator
      • 3.2.1 Static Latched Comparators
      • 3.2.2 Dynamic Latched Comparator
    • 3.3 Flash ADC Design Issues
      • 3.3.1 Reference-Ladder Bowing
      • 3.3.2 Capacitive Loading
      • 3.3.3 Input Signal Feed-through to Reference-Ladder
      • 3.3.4 Kickback Noise
      • 3.3.5 Bubbles (Sparkles) Generation
      • 3.3.6 Metastability
      • 3.3.7 Jitter Error
    • 3.4 Flash ADCs Research Background
    • 3.5 Conclusion
  • Chapter 4 A Novel Comparator Design for Flash ADC
    • 4.1 Introduction
    • 4.2 Modified CMOS Inverter for Flash ADC
      • 4.2.1 Small signal voltage gain
    • 4.3 Experimental Investigation of Modified Inverter
    • 4.4 DC Analysis
      • 4.4.1 Voltage Transfer Characteristic (VTC)
      • 4.4.2 Power Dissipation
      • 4.4.3 Variable Switching Voltage
      • 4.4.4 Propagation Delay and Dynamic Power Consumption
    • 4.5 Proposed Comparator
      • 4.5.1 Voltage Transfer Characteristic
      • 4.5.2 Simulation of Proposed Comparator
    • 4.6 Conclusion
  • Chapter 5 Design of Flash Analog to Digital Converters
    • 5.1 Introduction
    • 5.2 Reference-ladder Free Flash ADC Architecture
    • 5.3 Comparators array
    • 5.4 Encoder for Flash ADC design
      • 5.4.1 ROM Encoder
      • 5.4.2 Wallace-Tree Encoder
      • 5.4.3 MUX-Based Encoder
      • 5.4.4 Gray Encoding
    • 5.5 A 1-GS/s, 0.25-mW, 4-bit Flash ADC in UMC 180nm technology
      • 5.5.1 Variable Switching Voltages
      • 5.5.2 Thermometer to Binary Code Conversion
      • 5.5.3 Transient Simulation
      • 5.5.4 Simulation Results Comparison
    • 5.6 A 1-GS/s, 2.1mW, 6-bit Flash ADC in 65nm PTM technology
      • 5.6.1 Thermometer Code
      • 5.6.2 Transient Simulation
      • 5.6.3 Simulation Results Comparison
    • 5.7 Conclusion
  • Chapter 6 A Novel Power Efficient Design of Flash Architecture
    • 6.1 Introduction
    • 6.2 Proposed Power Efficient Design of 4-bit Flash ADC
      • 6.2.1 Proposed Comparator
      • 6.2.2 Working Principle of the Proposed Flash ADC
    • 6.3 Simulation of the proposed 4-bit Flash ADC
      • 6.3.1 Transient Response
      • 6.3.2 Result Summary

  Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)

  This work aims to present a novel reference-ladder free flash analog-to-digital converter (ADC) architecture, addressing the limitations of traditional flash ADC designs. The primary objective is to develop a power-efficient and high-speed ADC solution by eliminating the reference-ladder network, a key component that contributes to increased power consumption and complexity. The text explores various aspects of comparator design, encoder implementation, and architecture optimization.

  • Reference-Ladder Free Flash ADC Architecture
  • Power-Efficient Comparator Design
  • High-Speed ADC Implementation
  • Encoding Techniques for Flash ADCs
  • Performance Evaluation and Comparison

  Zusammenfassung der Kapitel (Chapter Summaries)

  Chapter 1 introduces the concept of analog-to-digital converters (ADCs) and presents the motivation and research objective behind the development of a reference-ladder free flash ADC architecture. Chapter 2 provides a comprehensive overview of the fundamentals of comparators and ADCs, including different ADC architectures and their key specifications. Chapter 3 delves into the existing literature on flash ADC design, highlighting key challenges and previous research efforts. Chapter 4 focuses on the design of a novel comparator, specifically tailored for flash ADC applications. Chapter 5 details the implementation of the reference-ladder free flash ADC architecture, exploring different encoder designs and showcasing the performance of two specific ADC implementations. Chapter 6 presents a power-efficient design of a 4-bit flash ADC, leveraging the novel comparator design and architecture optimization.

  Schlüsselwörter (Keywords)

  Analog-to-digital converter (ADC), flash ADC, reference-ladder free, comparator design, power efficiency, high-speed, encoder, thermometer code, binary code conversion, simulation, performance evaluation.

Details

• College: Manipal University Jaipur
• Grade: 10
• Author: Gulrej Ahmed (Author)
• Publication Year: 2021
• Pages: 85
• Catalog Number: V1160930
• ISBN (eBook): 9783346564108
• ISBN (Book): 9783346564115
• Language: English
• Tags: reference-ladder free flash analog digital converter architecture